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engineering specification type 15.0 xga color tft/lcd module model name:N150X4-L05 document control number : oem N150X4-L05-01 note:specification is subject to change without notice. consequently it is better to contact to international display technology before proceeding with the design of your product incorporating this module. sales support international display technology engineering specification (c) copyright international display technology 2002 all rights reserved. february 03,2003 oem N150X4-L05-01 1/29
i contents i contents ii record of revision 1.0 handling precautions 2.0 general description 2.1 characteristics 2.2 functional block diagram 3.0 absolute maximum ratings 4.0 optical characteristics 5.0 signal interface 5.1 connectors 5.2 interface signal connector 5.3 interface signal description 5.3.1 e-edud 5.4 interface signal electrical characteristics 5.4.1 signal electrical characteristics for lvds receiver 5.4.2 lvds receiver internal circuit 5.4.3 recommended guidelines for motherboard pcb design and cable selection 5.5 signal for lamp connector 6.0 pixel format image 7.0 parameter guide line for cfl inverter 8.0 interface timings 8.1 timing characteristics 8.2 timing definition 9.0 power consumption 10.0 power on/off sequence 11.0 mechanical characteristics 12.0 national test lab requirement engineering specification (c) copyright international display technology 2002 all rights reserved. february 03,2003 oem N150X4-L05-01 2/29
ii record of revision first edition for customer. based on internal spec."n150x4-ipi-01" all oem N150X4-L05-01 february 03,2003 summary page document revision date engineering specification (c) copyright international display technology 2002 all rights reserved. february 03,2003 oem N150X4-L05-01 3/29
1.0 handling precautions if any signals or power lines deviate from the power on/off sequence, it may cause shorten the life of the lcd module. the lcd panel and the cfl are made of glass and may break or crack if dropped on a hard surface, so please handle them with care. cmos ics are included in the lcd panel. they should be handled with care, to prevent electrostatic discharge. do not press the reflector sheet at the lcd module to any directions. do not stick the adhesive tape on the reflector sheet at the back of the lcd module. please handle with care when mount in the system cover. mechanical damage for lamp cable/lamp connector may cause safety problems. small amount of materials having no flammability grade is used in the lcd module. the lcd module should be supplied by power complied with requirements of limited power source (2.5, iec60950 or ul60950), or be applied exemption conditions of flammability requirements (4.7.3.4, iec60950 or ul60950) in an end product. the lcd module is designed so that the cfl in it is supplied by limited current circuit (2.4, iec60950 or ul60950). the fluorescent lamp in the liquid crystal display(lcd) contains mercury. do not put it in trash that is disposed of in landfills. dispose of it as required by local ordinances or regulations. never apply detergent or other liquid directly to the screen. wipe off water drop immediately. long contact with water may cause discoloration or spots. when the panel surface is soiled, wipe it with absorbent cotton or other soft cloth; do not use solvents or abrasives. do not touch the front screen surface in your system, even bezel. gently wipe the covers and the screen with a soft cloth. the information contained herein may be changed without prior notice. it is therefore advisable to contact international display technology before proceeding with the design of equipment incorporating this product. the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by international display technology for any infringements of patents or other right of the third partied which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of international display technology or others. engineering specification (c) copyright international display technology 2002 all rights reserved. february 03,2003 oem N150X4-L05-01 4/29
2.0 general description this specification applies to the type 15.0 color tft/lcd module 'N150X4-L05'. this module is designed for a display unit of a notebook style personal computer. the screen format and electrical interface are intended to support the xga (1024(h) x 768(v)) screen. support color is native 262k colors ( rgb 6-bit data driver ). all input signals are lvds(low voltage differential signaling) interface compatible. this module does not contain an inverter card for backlight. engineering specification (c) copyright international display technology 2002 all rights reserved. february 03,2003 oem N150X4-L05-01 5/29
2.1 characteristics the following items are characteristics summary on the table under 25 degree c condition: 100 mm cfl cable length 0 to +50 (operating) -20 to +60 (storage, shipping) temperature range [deg. c] native 262k colors ( rgb 6-bit data driver ) support color 4 pairs single lvds(single) electrical interface 317.3(w) x 242.0(h) x 6.2(d) typ. physical size [mm] 585 max. weight [grams] 3.8typ.(@icfl=6.0ma) cfl power consumption [watt] 1.6 typ. (all white pattern), 2.2 max (worst pattern) logic power consumption [watt] +3.3 v nominal input voltage [vdd] 60msec typ.; 120ms max. (@25degc) optical rise + fall time hardcoat only (no anti-glare treatment) surface treatment x:0.328 +/-0.030, y:0.337 +/- 0.030 color chromaticity cr>=10:1 h: +/-85 deg., v:+/-85 deg. typ. cr>=100:1 h: +/-40 deg., v:+/-40 deg. typ. viewing angle 400 : 1 typ. 300:1 min contrast ratio 200 typ. (screen center, icfl = 6.0ma) white luminance [cd/m 2 ] normally white display mode r.g.b. vertical stripe pixel arrangement 0.297(per one triad) x 0.297 pixel pitch [mm] 1024(x3) x 768 pixels h x v [pixels] 304.128(h) x 228.096(v) active area [mm] 38 screen diagonal [cm] specifications characteristics items engineering specification (c) copyright international display technology 2002 all rights reserved. february 03,2003 oem N150X4-L05-01 6/29
2.2 functional block diagram the following diagram shows the functional block of the type 15.0 color tft/lcd module. tft array/cell v dd lcd controlle r lcd drive card backli g ht unit 1024(r/g/b) x 768 gnd dc-dc converte r ref circuit y -driver x -drive r <4 p airs lvds> rxin1 rxin0 rxin2 rxclkin fi-xb30sl-hf10 bhsr-02vs-1 ( jst ) ccfl hi g h voltate ccfl low volta g e si g nal connecto r ccfl connector v dd v dd v dd eedid chip v eedid clceedid dataeedid engineering specification (c) copyright international display technology 2002 all rights reserved. february 03,2003 oem N150X4-L05-01 7/29
3.0 absolute maximum ratings absolute maximum ratings of the module is as follows : rectangle wave g ms 50 18 shock g hz 1.5 10-200 vibration (note 1) %rh 95 5 hst storage relative humidity (note 1) deg.c +60 -20 tst storage temperature (note 1) %rh 95 8 hop operating relative humidity (note 1) deg.c +50 0 top operating temperature a single pulse 20ma / 50ms - icflp cfl peak inrush current marms 7 - icfl cfl current vrms 2,000 - vinv lamp ignition voltage v vdd+0.3 -0.3 other inputs input voltage of signal v +4.0 -0.3 vdd supply voltage conditions unit max min s y mbol item note : 1. maximum wet-bulb should be 39 degree c and no condensation. engineering specification (c) copyright international display technology 2002 all rights reserved. february 03,2003 oem N150X4-L05-01 8/29
4.0 optical characteristics the optical characteristics are measured under stable conditions as follows under 25 degree c condition: 160min center 200typ. center white luminance (cd/m 2 ) icfl 6.0 ma +0.030 0.337 white y +0.030 0.328 white x - - blue y - - blue x - - green y - - green x (cie) - - red y chromaticity - - red x color (ms) 120 max. 60 rising + falling response time - 400 contrast ratio - - 85 85 vertical (upper) k 10 (lower) k:contrast ratio - - 85 85 horizontal (right) k 10 (left) viewing angle (degrees) note typ. specification conditions item engineering specification (c) copyright international display technology 2002 all rights reserved. february 03,2003 oem N150X4-L05-01 9/29
5.0 signal interface 5.1 connectors physical interface is described as for the connector on module. these connectors are capable of accommodating the following signals and will be following components. fi-x30m, fi-x30c2l mating receptacle/part number fi-xb30sl-hf10 type / part number jae manufacturer for signal connector connector name / designation sm02b-bhss-1 mating type / part number bhsr-02vs-1 type / part number jst manufacturer for lamp connector connector name / designation engineering specification (c) copyright international display technology 2002 all rights reserved. february 03,2003 oem N150X4-L05-01 10/29
5.2 interface signal connector nc 30 rxin2+ 15 nc 29 rxin2- 14 gnd 28 gnd 13 nc 27 rxin1+ 12 nc 26 rxin1- 11 gnd 25 gnd 10 nc 24 rxin0+ 9 nc 23 rxin0- 8 gnd 22 data eedid (note 2, 4) 7 nc 21 clk eedid (note 2, 4) 6 nc 20 reserved (note 1) 5 gnd 19 v edid (note 2, 3) 4 rxclkin+ 18 vdd 3 rxclkin- 17 vdd 2 gnd 16 gnd 1 signal name pin # signal name pin # note : 1. 'reserved' pins are not allowed to connect any other line. 2. this lcd module complies with "vesa enhanced extended display identification data standard release a, revision 1" and supports "eedid version 1.3". 3. v eedid power source shall be the limited current circuit which has not exceeding 1a. (reference document : "enhanced display data channel (e-ddc tm ) proposed standard", vesa) 4. both clk eedid line and data eedid line are pulled up with 10k ohm resistor to v eedid power source line at lcd panel, respectively. voltage levels of all input signals are lvds compatible (except vdd, eedid). refer to "signal electrical characteristics for lvds receiver", for voltage levels of all input signals. 5.3 interface signal description signal description ground gnd +3.3v power supply vdd lvds differential clock input rxclkin+, rxclkin- lvds differential data input (blue2-blue5, hsync, vsync, dsptmg) rxin2+, rxin2- lvds differential data input (green1-green5,blue0-blue1) rxin1+, rxin1- lvds differential data input (red0-red5, green0) rxin0+, rxin0- description signal name note : input signals shall be low or hi-z state when vdd is off. engineering specification (c) copyright international display technology 2002 all rights reserved. february 03,2003 oem N150X4-L05-01 11/29
eedid data data eedid eedid clock clk edid eedid 3.3 v power supply v eedid ground gnd power supply vdd horizontal sync:the signal is synchronized with dtclk . both active high/low signals are acceptable. hsync(h-s) vertical sync:the signal is synchronized to dtclk . both active high/low signal acceptable. vsync(v-s) when the signal is high, the pixel data shall be valid to be displayed. +dsptmg(dsp) data clock:the typical frequency is 65.0 mhz. the signal is used to strobe the pixel data and the dsptmg . dtclk blue data 5 (msb) blue data 4 blue data 3 blue data 2 blue data 1 blue data 0 (lsb) blue-pixel data: each blue pixel's brightness data consists of these 6 bits pixel data. +blue 5 +blue 4 +blue 3 +blue 2 +blue 1 +blue 0 green data 5 (msb) green data 4 green data 3 green data 2 green data 1 green data 0 (lsb) green-pixel data: each green pixel's brightness data consists of these 6 bits pixel data. +green 5 +green 4 +green 3 +green 2 +green 1 +green 0 red data 5 (msb) red data 4 red data 3 red data 2 red data 1 red data 0 (lsb) red-pixel data: each red pixcel's brightness data consists of these 6 bits pixel data. +red5 +red4 +red3 +red2 +red1 +red0 description signal name note : output signals except v eedid , clk eedid and data eedid from any system shall be hi-z state when vdd is off. engineering specification (c) copyright international display technology 2002 all rights reserved. february 03,2003 oem N150X4-L05-01 12/29
5.3.1 e-edid e-edid detail in this lcd module is in the following table. (note 1) checksum 7f no extension 00 extension flag 7e manufacturer p/n "n150x4" 00 00 00 fe 00 4e 31 35 30 58 34 0a 20 20 20 20 20 20 detailed timing / monitor description #4 6c - 7d manufactuerer name "idt" 00 00 00 fe 00 49 44 54 0a 20 20 20 20 20 20 20 20 20 detailed timing / monitor description #3 5a - 6b (note 1) detailed timing / monitor description #2 48 - 59 typical timing 64 19 00 40 41 00 26 30 18 88 36 00 30 e4 10 00 00 18 detailed timing / monitor description #1 36 - 47 unused 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 standard timing identification 26 - 35 unused 00 00 00 established timing 23 - 25 (note 1) color characteristics 19 - 22 active area : 30.41cm x 22.81cm, gamma : 2.2 80 1e 17 78 0a basic display parameter / features 14 - 18 ver1.3 01 03 edid structure version / revision 12 - 13 unused 00 year of manufacture 11 unused 00 week of manufacture 10 unused 00 00 00 00 id serial number 0c - 0f product code 0d 00 id product code 0a - 0b "idt" 24 94 id manufacturer name 08 - 09 header, fixed 00 ff ff ff ff ff ff 00 header 00 - 07 remark data (hex) description address (hex) note: 1.detail data contents shall be determined with concurrence between user and international display technology(idtech). engineering specification (c) copyright international display technology 2002 all rights reserved. february 03,2003 oem N150X4-L05-01 13/29
5.4 interface signal electrical characteristics 5.4.1 signal electrical characteristics for lvds receiver the lvds receiver equipped in this lcd module is compatible with ansi/tia/tia-644 standard. electrical characteristics vth - vtl = 200mv mv +50 -50 vcm common mode voltage offset vth - vtl = 200mv v 1.5 1.2 1.0 vcm common mode voltage mv 600 100 |vid| magnitude differential input voltage vcm=+1.2v mv -100 vtl differential input low threshold vcm=+1.2v mv +100 vth differential input high threshold conditions unit max typ min symbol parameter note : input signals shall be low or hi-z state when vdd is off. voltage definitions engineering specification (c) copyright international display technology 2002 all rights reserved. february 03,2003 oem N150X4-L05-01 14/29
measurement system timming requirements fc = 65mhz, tsu=thd=900ps ps/clk 20 tcjavg cycle modulation rate (note 4) fc = 65mhz, tsu=thd=900ps ps +150 -150 tccj cycle-to-cycle jitter (note 3) ps 500 thd data hold time (note 2) fc = 65mhz, tccj < 50ps, vth-vtl = 400mv, vcm = 1.2v, vcm = 0 ps 500 tsu data setup time (note 1) ns 20.00 15.38 14.93 tc cycle time mhz 67 65 50 fc clock frequency conditions unit max typ min symbol parameter note : 1. all values are at vdd=3.3v, ta=25 degree c. 2. see figure " timing definition " and " timing definition(detail a) " for definition. 3. jitter is the magnitude of the change in input clock period. 4. this specification defines maximum average cycle modulation rate in peak-to-peak transition within any 100 clock cycles. figure " cycle modulation rate " illustrates a case against this requirement. this specification is applied only if input clock peak jitter within any 100 clock cycles is greater than 300ps. engineering specification (c) copyright international display technology 2002 all rights reserved. february 03,2003 oem N150X4-L05-01 15/29
timing definition engineering specification (c) copyright international display technology 2002 all rights reserved. february 03,2003 oem N150X4-L05-01 16/29
timing definition(detail a) note: tsu and thd are internal data sampling window of receiver. trskm is the system skew margin; i.e., the sum of cable skew, source clock jitter, and other inter-symbol interference, shall be less than trskm. cycle modulation rate engineering specification (c) copyright international display technology 2002 all rights reserved. february 03,2003 oem N150X4-L05-01 17/29
5.4.2 lvds receiver internal circuit the following figure shows the internal block diagram of the lvds receiver. this lcd module equips termination resistors for lvds link. 5.4.3 recommended guidelines for motherboard pcb design and cable selection following the suggestions below will help to achieve optimal results. use controlled impedance media for lvds signals. they should have a matched differential impedance of 100 ohm. match electrical lengths between traces to minimize signal skew. isolate ttl signals from lvds signals. for cables, twisted pair, twin, or flex circuit with close coupled differential traces are recommended. engineering specification (c) copyright international display technology 2002 all rights reserved. february 03,2003 oem N150X4-L05-01 18/29
5.5 signal for lamp connector lamp low voltage 2 lamp high voltage 1 signal name pin # engineering specification (c) copyright international display technology 2002 all rights reserved. february 03,2003 oem N150X4-L05-01 19/29
6.0 pixel format image following figure shows the relationship of the input signals and lcd pixel format image. even and odd pair of rgb data are sampled at a time . 0 r 1 1022 1023 1st line 768th line g b r g r g b b rg b r gb rg b r g b r g b engineering specification (c) copyright international display technology 2002 all rights reserved. february 03,2003 oem N150X4-L05-01 20/29
7.0 parameter guide line for cfl inverter ta=25[deg. c] (note 4) [w] 3.8 cfl power consumption pcfl ta=25[deg. c] [vrms] 640 cfl voltage (reference) vcfl ta=0[deg. c] [vrms] 1,600 inverter ignition voltage vcfli ta=25[deg. c] (note 3) [khz] 70 40 cfl frequency fcfl ta=25[deg. c] (note 2,6) [ma] 20 cfl peak inrush current icflp ta=25[deg. c] (note 2,5) [marms] 7.0 6.0 3.0 cfl current icfl ta=25[deg. c] [cd/m 2 ] - - 200 - - white luminance (center) (l63) condition units max d.p (note 1) min parameter symbol note : 1. design point 2. if it exceeds min/max values, then"cfl life" , "on/off cycle", and "safety" will not be guaranteed. 3. cfl frequency should be carefully determined to avoid interference between inverter and tft lcd. 4. calculated value for reference (icfl x vcfl = pcfl). 5. it should be employed the inverter which has `duty dimming`, if icfl is less than 4[ma]. 6. duration: 50msec max engineering specification (c) copyright international display technology 2002 all rights reserved. february 03,2003 oem N150X4-L05-01 21/29
the following chart is luminance versus lamp current for your reference. engineering specification (c) copyright international display technology 2002 all rights reserved. february 03,2003 oem N150X4-L05-01 22/29
8.0 interface timings basically, interface timings should match the vesa 1024x768 / 60 hz (vg901101) manufacturing guide line timing. these timings described here are not actual input timings of lcd module but output timings of sn75lvds86dgg(texas instruments) or equivalent. 8.1 timing characteristics 1 tx 63 29 7 v-sync back porch vbp tx 3 1 v-sync front porch vfp tx 6 1 v-sync width vw hz 61 60 55 frame rate vsync tx 768 768 768 y active time tacy tx 1023 806 777 y total time ty tck 24 0 h front porch hfp 2 tck 510 160 8 h back porch hbp 2 tck 136 8 h-sync width hsw khz 48.363 h frequency hsync tck 1024 1024 1024 x active time tacx tck 2047 1344 1206 x total time tx nsec 20.00 15.38 14.93 dtclk cycle time tck mhz 67.00 65.00 50.00 dtclk frequency fdck note unit max typ min symbol note1 : vbp should be static. note2 : hsw+hbp> 32 [tck] - the timing interval between v-sync falling edge and h-sync rising edge should be fixed between each v-frame.(v-sync and h-sync polarity are assumed to be positive in this case.) engineering specification (c) copyright international display technology 2002 all rights reserved. february 03,2003 oem N150X4-L05-01 23/29
8.2 timing definition 1344 dot 136 dot 160 dot 24 dot 1024 dot h-sync dsptmg 38h 3h 29h 6h 768h v-sync dsptmg engineering specification (c) copyright international display technology 2002 all rights reserved. february 03,2003 oem N150X4-L05-01 24/29
9.0 power consumption input power specifications are as follows; [mvp-p] 100 allowable logic/lcd drive ri pp le volta ge vddrp max pattern, vdd=3.0[v] [ma] 640 (tbd) all black pattern, vdd=3.3[v] [ma] 490 (tbd) vdd current idd max. pattern, vdd=3.6[v] [w] 2.2 (tbd) all black pattern vdd=3.3 [ v ] [w] 1.6 ( tbd ) vdd power pdd load capacitance 20[uf] [v] 3.6 3.3 3.0 logic/lcd drive volta g e vdd condition units max t yp min parameter symbol engineering specification (c) copyright international display technology 2002 all rights reserved. february 03,2003 oem N150X4-L05-01 25/29
10.0 power on/off sequence vdd power and lamp on/off sequence is as follows. interface signals are also shown in the chart. signals from any system shall be hi-z state or low level when vdd is off. 90% 10% 10% 10% 90% 0.1ms min. 0 min. 0 min. 0 v 0 v vdd signals 10% 10% 200ms min. 0 min. 0 v lamp on 10% 10% 30ms max. 30ms min. engineering specification (c) copyright international display technology 2002 all rights reserved. february 03,2003 oem N150X4-L05-01 26/29
11.0 mechanical characteristics engineering specification (c) copyright international display technology 2002 all rights reserved. february 03,2003 oem N150X4-L05-01 27/29
engineering specification (c) copyright international display technology 2002 all rights reserved. february 03,2003 oem N150X4-L05-01 28/29
12.0 national test lab requirement the display module will satisfy all requirements for compliance to ul 60950, 3rd edition u.s.a. information technology equipment can/csa-c22.2 no. 60950-00 canada, information technology equipment iec 60950 (3rd. ed.) international, information technology equipment en 60950 (3rd. ed.) international, information technology equipment (european norm for iec60950) ****** end of page ****** engineering specification (c) copyright international display technology 2002 all rights reserved. february 03,2003 oem N150X4-L05-01 29/29

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